In the construction of a pin grid array in the prior art for use in packaging an IC chip to enable it to be connected to a printed circuit board, it is customary to provide a multilayer structure fabricated by use of cofired technology. Such a multilayer structure is typically formed from a dozen or more individual green ceramic layers including a bottom layer provided with a plurality of via holes filled with tungsten paste and a top layer screen printed with tungsten paste to provide bonding pads thereon. Each of the layers also has its upper surface screen printed with tungsten paste to provide conductive paths thereon. Moreover, each of the upper layers is provided with interlevel vias filled with tungsten paste and located for electrically interconnecting the conductive paths on the successive layers and, therefore, each of the tungsten filled vias on the bottom layer to one of the bonding pads on the top layer. These individual green ceramic layers are stacked, laminated under pressure and cofired to create a monolithic structure. Pins are then brazed to the ends of the tungsten filled vias on the lower surface of the bottom layer and an IC chip is mounted with contact pads on the face thereof wire bonded to the bonding pads on the top layer.
In its continued effort to make digital processors smaller, faster and more powerful, the industry finds that the above cofired construction of a pin grid array for providing connections between an IC chip and a printed circuit board has many disadvantages. Among these is that the shrinkage of the green ceramic layers when cofired throws off the registration of the tungsten filled vias on the bottom layer and the interlevel tungsten filled vias on the upper layers relative to the locations of the conductive paths provided on the upper surfaces of the respective layers as needed to electrically interconnect the pins on the bottom layer to the bonding pads provided on the top layer. Thus, because of the lack of registration, the areas of the tungsten pads that are provided on the surfaces of the respective layers to interconnect the interlevel tungsten filled vias have to be made larger thereby taking up space on each of the surfaces so that a lesser number of conductive paths can be laid down thereon. This requires many ceramic layers on the multilayer structure to provide for depositing all the connecting paths needed between the bottom pins and the top bonding pads for an IC chip, especially when the IC chip has a large number of inputs and outputs.
Another reason that requires the multilayer structure to have even more ceramic layers is because, when a cofired process is used, the conductive paths are formed with a tungsten paste and the lengths of the interconnecting conductive paths are very long. As a result, the electrical resistance of these conductive paths between the pins and the bonding pads is very high. In order to minimize the resistance it is necessary to widen the tungsten paths and this takes up space and further reduces the density by which the conductive paths can be laid down. Now this widening of the tungsten conductive paths to minimize their resistance has a further deleterious effect on the electrical performance of the pin grid array. This is because of the need to provide the larger area pads on the ends of the tungsten conductive paths to enable them to connect to the interlevel tungsten filled vias which have lost their registration due to the shrinkage of the green ceramic layers when cofired. Such large area pads add interlayer capacitance which slows down the speed of operation of the pin grid array so that the IC chip mounted thereon cannot be operated at the high speed for which it was designed. It should now be clear that a pin grid array used as a carrier for a high density, high speed IC chip cannot be practically provided by the cofiring process.